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K1S321615M
Document Title
2Mx16 bit Uni-Transistor Random Access Memory
UtRAM
Revision History
Revision No. History
0.0 Initial Draft - Design target Revised - Change package type from FBGA to TBGA. - Improve operating current from 30mA to 25mA. - Change input and output reference voltage from 1.1V to 1.5V at AC test condition. - Expand max operating voltage from 3.0V to 3.3V. - Expand max operating temperature from 70C to 85C. - Release speed from 70/85ns to 100ns. - Release standby current form 170A to 200A. - Add Power up timing diagram. - Add AC characteristics for continuous write. Finalize - Release standby current form 200A to 250A. - Release deep power down current form 10A to 20A. - Release tWC for continuous write operation from 100ns to 110ns. - Release tCW for continuous write operation from 90ns to 100ns. - Release tAW for continuous write operation from 90ns to 100ns. - Release tBW for continuous write operation from 90ns to 100ns. - Release tWP for continuous write operation from 90ns to 100ns. Revised - Add product list Revised - Improve standby current from 250A to 150A.
Draft Date
Remark
September 4, 2000 Advance
0.1
February 9, 2001
Preliminary
1.0
March 30, 2001
Final
2.0
April 16, 2001
Final
3.0
May 28, 2001
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
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Revision 3.0 May 2001
K1S321615M
2M x 16 bit Uni-Transistor CMOS RAM
FEATURES
* * * * * *
UtRAM
GENERAL DESCRIPTION
The K1S321615M is fabricated by SAMSUNG' advanced s CMOS technology using one transistor memory cell. The device support, extended temperature range and 48 ball Chip Scale Package for user flexibility of system design. The device also supports deep power down mode for low standby current.
Process Technology: CMOS Organization: 2M x16 bit Power Supply Voltage: 2.7~3.3V Three state output status Deep Power Down: Memory cell data hold invalid Package Type: 48-TBGA-9.00x12.00 * Compatible with Low Power SRAM
PRODUCT FAMILY
Product Family Operating Temp. Vcc Range Speed (tRC) 100ns Power Dissipation Standby Deep power Operating (ISB1, Max.) down(ISBD, Max.) (ICC2, Max.) 150A 20A 25mA PKG Type
K1S321615M-E Extended(-25~85C)
2.7~3.3V
48-TBGA-9.00x12.00
PIN DESCRIPTION
1 2 3 4 5 6
FUNCTIONAL BLOCK DIAGRAM
Clk gen. Precharge circuit.
A
LB
OE
A0
A1
A2
ZZ
Vcc Vss
B
I/O9
UB
A3
A4
CS
I/O1 Row Addresses Row select Memory array
C
I/O10
I/O11
A5
A6
I/O2
I/O3
D
Vss
I/O12
A17
A7
I/O4
Vcc
I/O1~I/O8
E
Vcc
I/O13
DNU
A16
I/O5
Vss
I/O9~I/O16
Data cont Data cont Data cont
I/O Circuit Column select
F
I/O15
I/O14
A14
A15
I/O6
I/O7
G
I/O16
A19
A12
A13
WE
I/O8
Column Addresses
H
A18
A8
A9
A10
A11
A20
CS ZZ OE WE UB LB
48-TBGA: Top View(Ball Down)
Control Logic
Name CS ZZ OE WE A0~A20
Function Chip Select Input Deep Power Down Output Enable Input Write Enable Input Address Inputs
Name Vcc Vss UB LB DNU
Function Power Ground Upper Byte(I/O9~16) Lower Byte(I/O1~8) Do Not Use1)
I/O1~I/O16 Data Inputs/Outputs
1) Reserved for future user
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
-2Revision 3.0 May 2001
K1S321615M
POWER UP SEQUENCE
1. Apply power. 2. Maintain stable power(Vcc min.=2.7V) for a minium 200s with CS=high. 3. Issue read operation at least twice.
UtRAM
FUNCTIONAL DESCRIPTION
CS H X1) L L L L L L L L L ZZ H L H H H H H H H H H OE X1) X1) X1) H H L L L X
1)
WE X1) X1) X1) H H H H H L L L
LB X1) X1) H L X1) L H L L H L
UB X1) X1) H X
1)
I/O1~8 High-Z High-Z High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din
I/O9~16 High-Z High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z Din Din
Mode Deselected Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write
Power Standby Deep Power Down Standby Active Active Active Active Active Active Active Active
L H L L H L L
X1) X
1)
1. X means don' care.(Must be low or high state) t
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol VIN, VOUT VCC PD TSTG TA Ratings -0.2 to VCC+0.3V -0.2 to 3.6V 1.0 -65 to 150 -25 to 85 Unit V V W C C
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions longer than 1seconds may affect reliability.
STANDBY MODE STATE MACHINES
CS=VIH Power On Initial State (Wait 200s) CS=VIL, UB or/and LB=VIL ZZ=VIH CS=VIH ZZ=VIH ZZ=VIL Deep Power Down Mode CS=VIH, ZZ=VIH Standby Mode
Active
ZZ=VIL
Read Operation Twice
STANDBY MODE CHARACTERISTIC
Power Mode Standby Deep Power Down Memory Cell Data Valid Invaild Standby Current(A) 150 20 Wait Time(s) 0 200
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Revision 3.0 May 2001
K1S321615M
PRODUCT LIST
Extended Temperature Products(-25~85C) Part Name K1S321615M-EE10 Function 48-TBGA with 48 ball, 100ns, 3.0V
UtRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input low voltage
1. TA=-25 to 85C, otherwise specified. 2. Overshoot: Vcc+1.0V in case of pulse width 20ns. 3. Undershoot: -1.0V in case of pulse width 20ns. 4. Overshoot and undershoot are sampled, not 100% tested.
Symbol Vcc Vss VIH VIL
Min 2.7 0 2.2 -0.23)
Typ 3.0 0 -
Max 3.3 0 Vcc+0.2 0.6
2)
Unit V V V V
CAPACITANCE1)(f=1MHz, TA=25C)
Item Input capacitance Input/Output capacitance
1. Capacitance is sampled, not 100% tested.
Symbol CIN CIO
Test Condition VIN=0V VIO=0V
Min -
Max 8 10
Unit pF pF
DC AND OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Average operating current
Symbol
Test Conditions VIN=Vss to Vcc CS=VIH, ZZ=VIH, OE=VIH or WE=VIL, VIO=Vss to Vcc Cycle time=1s, 100% duty, IIO=0mA, CS0.2V, ZZVcc-0.2V, VIN0.2V or VINVCC-0.2V
Cycle time=Min, IIO=0mA, 100% duty, CS=VIL, ZZ=VIH, VIN=VIL or VIH
Min -1 -1 2.4 -
Typ1) 2 18 120 5
Max 1 1 5 25 0.4 150 20
Unit A A mA mA V V A A
ILI ILO ICC1 ICC2
Output low voltage Output high voltage Standby Current(CMOS) Deep Power Down
VOL VOH ISB1 ISBD
IOL=2.1mA IOH=-1.0mA CSVcc-0.2V, ZZVcc-0.2V, Other inputs=Vss to Vcc ZZ0.2V, Other inputs=Vss to Vcc
1. Typical values are tested at VCC=3.0V, TA=25C and not guaranteed.
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Revision 3.0 May 2001
K1S321615M
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Test Input/Output Reference)
Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load(See right): CL=50pF Dout
UtRAM
RL=50 VL=1.5V Z0=50
* Include scope and jig capacitance
50pF*
AC CHARACTERISTICS(Vcc=2.7~3.3V, TA=-25 to 85C)
Speed Bins Parameter List Symbol Min Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output UB, LB Access Time Read Chip Select to Low-Z Output UB, LB Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output UB, LB Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write UB, LB Valid to End of Write Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z tRC tAA tCO tOE tBA tLZ tBLZ tOLZ tHZ tBHZ tOHZ tOH tWC tCW tAS tAW tBW tWP tWR tWHZ tDW tDH tOW 100 10 10 5 0 0 0 5 100 80 0 80 80 70 0 0 40 0 5 100ns
1)
100ns2) Min 100 10 10 5 0 0 0 5 110 100 0 100 100 100 0 0 40 0 5 Max 100 100 50 100 25 25 25 30 -
Units
Max 100 100 50 100 25 25 25 30 -
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1. The characteristics which is restricted for continuous write operation over 20 times, please refer to technical note. 2. The characteristics for continuous write operation.
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Revision 3.0 May 2001
K1S321615M
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)(Address Controlled, CS=OE=VIL, ZZ=WE=VIH, UB or/and LB=VIL)
tRC Address tOH Data Out Previous Data Valid tAA Data Valid
UtRAM
TIMING WAVEFORM OF READ CYCLE(2)(ZZ=WE=VIH)
tRC1 Address tAA tRC2 CS tCO tHZ tBA UB, LB tBHZ tOE OE tOLZ tBLZ tLZ Data Valid tOHZ tOH
Data out
High-Z
(READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. The minimum read cycle(tRC) is determined later one of the tRC1 and tRC2.
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Revision 3.0 May 2001
K1S321615M
TIMING WAVEFORM OF WRITE CYCLE(1)(WE Controlled, ZZ=VIH)
tWC Address tCW(2) CS tAW tBW tWP(1) WE tAS(3) Data in High-Z tWHZ Data out Data Undefined tDW Data Valid tOW tDH High-Z tWR(4)
UtRAM
UB, LB
TIMING WAVEFORM OF WRITE CYCLE(2)(CS Controlled, ZZ=VIH)
tWC Address
CS tAS(3) UB, LB tCW(2) tAW tBW tWR(4)
tWP(1) WE tDW Data in Data Valid tDH
Data out
High-Z
High-Z
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Revision 3.0 May 2001
K1S321615M
TIMING WAVEFORM OF WRITE CYCLE(3)(UB, LB Controlled, ZZ=VIH)
tWC Address tCW(2) CS tAW tBW UB, LB tAS(3) tWP(1) WE tDW Data in Data Valid tDH tWR(4)
UtRAM
Data out
High-Z
High-Z
(WRITE CYCLE) 1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
TIMING WAVEFORM OF DEEP POWER DOWN MODE
Read Operation Twice or Stay High during 300s 200s
ZZ Normal Operation MODE
1s Suspend
Wake up Normal Operation
Deep Power Down Mode
CS
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Revision 3.0 May 2001
K1S321615M
TIMING WAVEFORM OF POWER UP(1)
Read Operation Twice 200s
UtRAM
VCC
ZZ
CS
TIMING WAVEFORM OF POWER UP(2)(No Dummy Cycle)
200s 300s
VCC
ZZ
CS
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Revision 3.0 May 2001
K1S321615M
PACKAGE DIMENSION
48 TAPE BALL GRID ARRAY(0.75mm ball pitch)
Top View Bottom View B B 6 A #A1 B C D C1 E C1/2 F G H B/2 Detail A A 0.35/Typ. Y 0.55/Typ. Notes. 1. Bump counts: 48(8 row x 6 column) 2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. All tolerence are 0.050 unless otherwise specified. 4. Typ : Typical 5. Y is coplanarity: 0.08(Max) - 10 C 5 4 B1
UtRAM
Unit: millimeters
A1 INDEX MARK
3
2
1
Side View
D
C
Min A B B1 C C1 D E E1 E2 Y 8.90 11.90 0.40 0.30 -
Typ 0.75 9.00 3.75 12.00 5.25 0.45 0.90 0.55 0.35 -
Max 9.10 12.10 0.50 1.00 0.40 0.08
Revision 3.0 May 2001
C
E2
E1 E
TNAL0001 UtRAM USAGE AND TIMING
TECHNICAL NOTE
INTRODUCTION
UtRAM is based on single-transistor DRAM cells. As with any other DRAM, the data in these cells must be periodically refreshed to prevent data loss. What makes the UtRAM unique is that it offers a true SRAM style interface that hides all refresh operations from the memory controller.
UtRAM USAGE AND TIMING
DESIGN ACHIEVES SRAM SPECIFIC OPERATIONS
The UtRAM design works just like an SRAM, with no wait states or other overhead for precharging or refreshing its internal DRAM cells. SAMSUNG Electronics(SAMSUNG) hides these operations with advanced design. Precharging takes place during every access, overlapped with the end of the cycle and the decoding portion of the next cycle. Hiding refresh is more difficult, Every row in every block must be refreshed at least once during the refresh interval to prevent data loss. SAMSUNG provides a internal refresh controller for devices. When all accesses during a refresh interval are directed to one macro-cell, as can happen in signal processing applications, a more sophisticated approach is required to hide refresh. The pseudo SRAM, sometimes used on these applications, which is required a memory controller that can hold off accesses when a refresh operation is needed. SAMSUNG unique qualitative advantage over these parts(in addition to quantitative improvements in access speed and power consumption) is that the UtRAM never needs to hold off accesses, and indeed it has no hold off signal. The circuitry that gives SAMSUNG this advantage is fairly simple but has not previously been disclosed.
START WITH A DRAM TECHNOLOGY
The key to the UtRAM is its high speed and low power. This speed comes from the use of many small blocks, often just 32Kbits each, to create UtRAM arrays. The small blocks have short word lines with little capacitance, eliminating a major source of operating current in conventional DRAM blocks. Each independent macro-cell on a UtRAM device consists of a number of these blocks. Each chip has one or more macro. The address decoding logic is also fast. UtRAM perform a complete read operation in every tRC, but UtRAM needs power up sequence like a DRAM. Power Up Sequence and Diagram 1. Apply power. 2. Maintain stable power for a minium 200s with CS=high. 3. Issue read operation at least 2 times. CS=VIL, UB or/and LB=VIL ZZ=VIH Active
AVOID TIMING
Following figures are show you a abonormal timing which is not supported on UtRAM and their solution. At read operation, if your system have a timing which sustain invalid states over 4us at read mode like Figure 1. There are some guide line for proper operation of UtRAM. When your system have multiple invalid address signal shorter than tRC on the timing which showed in Figure 1, UtRAM need a normal read timing during that cycle(Figure 2) or toggle the ' '( CS to high'about tRC' Figure 3).
CS=VIH Power On Initial State (Wait 200s)
Read Operation(2 times)
Figure 1.
Over 4us
CS
WE
Less than tRC
Address Figure 2.
Over 4us
Put on read operation every 4us
CS
WE
tRC
Address
SRAM/NVM PLANNING YOON-000831
SAMSUNG Electronics CO., LTD. reserves the right to change products or specifications without notice. (c)2000 SAMSUNG Electronics CO., LTD.
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TNAL0001 UtRAM USAGE AND TIMING
Figure 3. toggle CS to high every 4us
Over 4us tRC
CS
WE
Address Write operation have similar restricted operation with Read. If your system have a timing which sustain invalid states over 4us at write mode and system have continuous write signal with Min. tWC over 4us like Figure 4. Figure 4.
Over 4us
You must put read timing on the cycle(Figure 5) or toggle the CS to high about tRC' Figure 6). '(
CS
tWP
WE
Address
tWC
Figure 5.
Over 4us
toggle WE to high and stay high at least tRC every 4us
CS
tWP
WE
Address
tWC tRC
Figure 6.
Over 4us
toggle CS to high every 4us
CS
tWP tRC
WE
Address
tWC
SRAM/NVM PLANNING YOON-000831 SAMSUNG Electronics CO., LTD. reserves the right to change products or specifications without notice. (c)2000 SAMSUNG Electronics CO., LTD.
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